library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.ESD2004_types.all;

entity alu is
	    port(  in_a         : in  std_logic_vector(7 downto 0);
                   in_b         : in  std_logic_vector(7 downto 0);
                   op           : in  Alu_op;
                   result       : out std_logic_vector(7 downto 0);
                   overflow     : out std_logic );
end alu;


architecture beh of alu is

  signal temp : std_logic_vector(7 downto 0);
  
begin

process ( in_a , in_b , op )

begin
	case op is
		
		-- 0000 
		when alu_add => temp <= signed(in_a) + signed(in_b) ;
												
		--0001
		when alu_sub => temp <= signed(in_a) - signed(in_b) ;				
		
		--0010
		when alu_and => temp <= in_a and in_b ;
		
		--0011			 
		when alu_or =>  temp <= in_a or in_b ;
		
		--0100
		when alu_not => temp <= not in_a;
		
		--0101
		when alu_xor => temp <= in_a xor in_b ;
		
		--0110
		when alu_sgt => if signed(in_a) > signed(in_b) then
					temp <=conv_std_logic_vector(1,8);
				else 
					temp <=conv_std_logic_vector(0,8);
				end if;						

                --0111
		when alu_sge => if signed(in_a) >= signed(in_b) then
					temp <=conv_std_logic_vector(1,8);
				else 
					temp <=conv_std_logic_vector(0,8);
				end if;

		--1000
		when alu_slt => if signed(in_a) < signed(in_b) then
					temp <=conv_std_logic_vector(1,8);
				else 
					temp <=conv_std_logic_vector(0,8);
				end if;                    	
					
		when alu_sle => if signed(in_a) <= signed(in_b) then
					temp <=conv_std_logic_vector(1,8);
				else 
					temp <=conv_std_logic_vector(0,8);
				end if;

		when others => temp <= in_a;
	end case;
   end process;

   process(in_a,in_b,op,temp)
   begin
     if op = alu_add then
          if ( in_a(7) /= in_b(7) )  or
                ( in_a(7) = temp(7) ) then
                overflow <= '0';        
             else
                overflow <= '1';        
             end if;
                
       elsif op = alu_sub then
             if ( in_a(7) = in_b(7) )  or
                ( in_a(7) = temp(7) ) then
                overflow <= '0';
             else
                overflow <= '1';
             end if;                     
       else
             overflow <= '0';
       end if;
   end process;
        
   result   <= temp;
  

end beh;