LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY lpm;
USE lpm.lpm_components.ALL;

entity data_memory is 
port( CK          : in std_logic;
	  OEN,WEN,CSN  : in std_logic; -- Output enable, Write enable, Chip select.
								   -- Sono tutti segnali di controllo attivi bassi, 
								   -- tipici delle memorie on-chip. Nel nostro caso CS e' sempre attivo!
      A : in std_logic_vector(7 downto 0);
      D : in std_logic_vector(7 downto 0);
      Q : out std_logic_vector(7 downto 0) ); 
end data_memory;
	
architecture memory_b of data_memory is

signal uno    : std_logic :='1';
signal zero   : std_logic := '0';
signal we,ckn : std_logic;

component lpm_ram_dq
generic( lpm_width: positive := 8;
         lpm_widthad: positive :=8;
         lpm_outdata: string:="UNREGISTERED";
         lpm_file: string:="data_memory.mif";
		 use_eab: string:="on" );

port ( data    : in  std_logic_vector(LPM_WIDTH-1 downto 0);
       address : in  std_logic_vector(LPM_WIDTHAD-1 downto 0);
       inclock : in  std_logic := '0';
       we      : in  std_logic;
       q       : out std_logic_vector(LPM_WIDTH-1 downto 0) );
end component;

begin
	data_mem: lpm_ram_dq
      PORT MAP ( data => D,  
		 address => A,
		 inclock => CKN,  
		 we => we,
                 q => Q);

	we  <= not WEN;
	ckn <= not ck; -- Scegliamo di campionare il clk sul fronte negativo!

end memory_b;