-----------------------------------------------------------
--Decode Inst ---------------------------------------------
-----------------------------------------------------------

library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
   use work.ESD2004_types.all;

entity Decode_instr is
port(   instr               : in Std_logic_vector(15 downto 0);
        rs1,rs2,rd          : out std_logic_vector(2 downto 0);
        alu_operation       : out Alu_op; 
        jump_operation      : out Jump_op;
        shift_operation     : out Shift_op;
        wb_mux              : out Std_logic_vector(1 downto 0);
        imm_mux             : out std_logic;
        Immediate           : out Std_logic_vector(7 downto 0);
        mr,mw               : out std_logic );
end Decode_instr;

architecture beh of Decode_instr is
begin
	process(instr)
	begin

	  case instr(15 downto 11) is
		
		when "00000" => -- ADD
						rd  <= instr(8 downto 6);
						rs1 <= instr(5 downto 3);
						rs2 <= instr(2 downto 0);
						jump_operation  <= j_normal; 
						alu_operation   <= alu_add;
						shift_operation <= sh_sll;
						wb_mux          <= "00";  -- Alu
						imm_mux         <= '0'; -- No Immediate
                                                immediate       <= (others => '0');
                                                mr <= '0'; mw <= '0';

		when "00001" => -- SUB
						rd  <= instr(8 downto 6);
						rs1 <= instr(5 downto 3);
						rs2 <= instr(2 downto 0);
						jump_operation  <= j_normal;
						alu_operation   <= alu_sub;
						shift_operation <= sh_sll;
						wb_mux          <= "00"; -- Alu
						imm_mux         <= '0'; -- No Immediate
						immediate       <= (others => '0');
                                                mr <= '0'; mw <= '0';

		when "01000" => -- ADDI
						rd  <= instr(10 downto 8);
						rs1 <= instr(10 downto 8);
						rs2 <= "000";
						jump_operation  <= j_normal; 
						alu_operation   <= alu_add;
						shift_operation <= sh_sll;
						wb_mux          <= "00";  -- Alu
						imm_mux         <= '1'; -- Immediate
                                                immediate       <= instr(7 downto 0);
                                                mr <= '0'; mw <= '0';

		when "01001" => -- SUBI
						rd  <= instr(10 downto 8);
						rs1 <= instr(10 downto 8);
						rs2 <= "000";
						jump_operation  <= j_normal;
						alu_operation   <= alu_sub;
						shift_operation <= sh_sll;
						wb_mux          <= "00"; -- Alu
						imm_mux         <= '1'; -- Immediate
						immediate       <= instr(7 downto 0);
                                                mr <= '0'; mw <= '0';

		when "00010" => -- AND
						rd  <= instr(8 downto 6);
						rs1 <= instr(5 downto 3);
						rs2 <= instr(2 downto 0);
						jump_operation  <= j_normal; 
						alu_operation   <= alu_and;
						shift_operation <= sh_sll;
						wb_mux          <= "00";  -- Alu
						imm_mux         <= '0'; -- No Immediate
                                                immediate       <= (others => '0');
                                                mr <= '0'; mw <= '0';
                                                
		when "00011" => -- OR
						rd  <= instr(8 downto 6);
						rs1 <= instr(5 downto 3);
						rs2 <= instr(2 downto 0);
						jump_operation  <= j_normal; 
						alu_operation   <= alu_or;
						shift_operation <= sh_sll;
						wb_mux          <= "00";  -- Alu
						imm_mux         <= '0'; -- No Immediate
                                                immediate       <= (others => '0');
                                                mr <= '0'; mw <= '0';

		when "00100" => -- NOT
						rd  <= instr(8 downto 6);
						rs1 <= instr(5 downto 3);
						rs2 <= instr(2 downto 0);
						jump_operation  <= j_normal; 
						alu_operation   <= alu_not;
						shift_operation <= sh_sll;
						wb_mux          <= "00";  -- Alu
						imm_mux         <= '0'; -- No Immediate
                                                immediate       <= (others => '0');
                                                mr <= '0'; mw <= '0';
                                                                      
		when "00101" => -- SGE
						rd  <= instr(8 downto 6);
						rs1 <= instr(5 downto 3);
						rs2 <= instr(2 downto 0);
						jump_operation  <= j_normal; 
						alu_operation   <= alu_sge;
						shift_operation <= sh_sll;
						wb_mux          <= "00";  -- Alu
						imm_mux         <= '0'; -- No Immediate
                                                immediate       <= (others => '0');
                                                mr <= '0'; mw <= '0';

 		when "00110" => -- SGT
						rd  <= instr(8 downto 6);
						rs1 <= instr(5 downto 3);
						rs2 <= instr(2 downto 0);
						jump_operation  <= j_normal; 
						alu_operation   <= alu_sgt;
						shift_operation <= sh_sll;
						wb_mux          <= "00";  -- Alu
						imm_mux         <= '0'; -- No Immediate
                                                immediate       <= (others => '0');
                                                mr <= '0'; mw <= '0';

 		when "10000" => -- SB
						rd  <= "000";
						rs1 <= instr(10 downto 8);
						rs2 <= "000";
                                                
						jump_operation  <= j_normal; 
						alu_operation   <= alu_add;
						shift_operation <= sh_sll;
						wb_mux          <= "00";  -- Alu
						imm_mux         <= '1'; -- Immediate
                        immediate       <= instr(7 downto 0);
                        mr <= '0'; mw <= '1';

 		when "10001" => -- LB
						rd  <= instr(10 downto 8);
						rs1 <= "000";
						rs2 <= "000";
                                                
						jump_operation  <= j_normal; 
						alu_operation   <= alu_add;
						shift_operation <= sh_sll;
						wb_mux          <= "11";  -- Mem
						imm_mux         <= '1';  -- Immediate
                        immediate       <= instr(7 downto 0);
                        mr <= '1'; mw <= '0';                                                

 		when "10100" => -- BEQZ 
						rd  <= "000";
						rs1 <= instr(5 downto 3);
						rs2 <= "000";
						jump_operation  <= j_beqz; 
						alu_operation   <= alu_add;
						shift_operation <= sh_sll;
						wb_mux          <= "00";  -- Alu
						imm_mux         <= '0'; -- No Immediate
                                                immediate       <= instr(7 downto 0);
                                                mr <= '0'; mw <= '0';

 		when "10101" => -- BNEQZ 
						rd  <= "000";
						rs1 <= instr(10 downto 8);
						rs2 <= "000";
						jump_operation  <= j_bneqz; 
						alu_operation   <= alu_add;
						shift_operation <= sh_sll;
						wb_mux          <= "00";  -- Alu
						imm_mux         <= '0'; -- No Immediate
                                                immediate       <= instr(7 downto 0);
                                                mr <= '0'; mw <= '0';

 		when "10010" => -- J
						rd  <= "000";
						rs1 <= "000";
						rs2 <= "000";
						jump_operation  <= j_imm; 
						alu_operation   <= alu_add;
						shift_operation <= sh_sll;
						wb_mux          <= "00";  -- Alu
						imm_mux         <= '0'; -- No Immediate
                                                immediate       <= instr(7 downto 0);
                                                mr <= '0'; mw <= '0';

  		when "10011" => -- JR
						rd  <= "000";
						rs1 <= instr(10 downto 8);
						rs2 <= "000";
						jump_operation  <= j_reg; 
						alu_operation   <= alu_add;
						shift_operation <= sh_sll;
						wb_mux          <= "00";  -- Alu
						imm_mux         <= '0'; -- No Immediate
                                                immediate       <= (others => '0');
                                                mr <= '0'; mw <= '0';
                                                
                                                
		when others => -- Undefined operation (NOP)
						rd  <= "000";
						rs1 <= "000";
						rs2 <= "000";
						jump_operation  <= j_normal; 
						alu_operation   <= alu_add;
						shift_operation <= sh_sll;
						wb_mux          <= "00"; -- Alu
						imm_mux         <= '0'; -- No Immediate
						immediate       <= (others => '0');
                                                mr <= '0'; mw <= '0';
          end case;
       end process;	
end beh;