----------------------------------------------------------------------
-- PROCESSOR CORE ENTITY 
----------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.ESD2004_types.all;

entity ESD2004_core is
port( 
      ck,reset,enable      : in  std_logic; 
      I_ADDR               : out std_logic_vector(7 downto 0); 
      I_INSTR              : in  std_logic_vector(15 downto 0); 
      D_MR,D_MW            : out std_logic; 
      D_ADDR               : out std_logic_vector(7 downto 0); 
      D_DATAOUT            : out std_logic_vector(7 downto 0); 
      D_DATAIN             : in  std_logic_vector(7 downto 0);

      WB_REG   : out std_logic_vector(2 downto 0);
	  WB_VALUE : out std_logic_vector(7 downto 0)
); 
end ESD2004_core; 

architecture struct of ESD2004_core is

component Decode_PC 
port(   ck, reset, enable  : in std_logic;
        op                  : in Jump_op;
        Reg_in              : in Std_logic_vector(7 downto 0);
        Immediate           : in Std_logic_vector(7 downto 0);

        curr_pc             : out Std_logic_vector(7 downto 0) );
end component;

component Decode_instr 
port(   instr               : in  Std_logic_vector(15 downto 0);
        rs1,rs2,rd          : out std_logic_vector(2 downto 0);
        alu_operation       : out Alu_op; 
        jump_operation      : out Jump_op;
        shift_operation     : out Shift_op;
        wb_mux              : out Std_logic_vector(1 downto 0);
        imm_mux             : out std_logic;
        Immediate           : out Std_logic_vector(7 downto 0);
        mr,mw               : out std_logic );
end component;

component regfile 
    port(  ck     : in  Std_logic;
           reset  : in  Std_logic;
           ra     : in  Std_logic_vector(2 downto 0);
           a_out  : out Std_logic_vector(7 downto 0);
     	   rb     : in  Std_logic_vector(2 downto 0);
           b_out  : out Std_logic_vector(7 downto 0);
                           
    	   rd1    : in  Std_logic_vector(2 downto 0);
           d1_in  : in  Std_logic_vector(7 downto 0)  );    
end component;

component alu 
  port(  in_a         : in  std_logic_vector(7 downto 0);
         in_b         : in  std_logic_vector(7 downto 0);
         op           : in  Alu_op;
         result       : out std_logic_vector(7 downto 0);
         overflow     : out std_logic );
end component;

component shifter 
  port(  in_a         : in  std_logic_vector(7 downto 0);
         in_b         : in  std_logic_vector(7 downto 0);
         op           : in  Shift_op;
         result       : out std_logic_vector(7 downto 0) );
end component;

signal alu_operation     : alu_op;
signal jump_operation    : jump_op;
signal shift_operation   : shift_op;
signal curr_pc,immediate : std_logic_vector(7 downto 0);

signal rs1,rs2,rd : std_logic_vector(2 downto 0);
signal rf_out1,rf_out2,source1,source2,alu_out,shift_out,mem_out,rf_in : std_logic_vector(7 downto 0);
signal imm_mux : std_logic;
signal wb_mux  : std_logic_vector(1 downto 0);
signal mr,mw   : std_logic;

begin
	
-- CONTROL LOGIC ---------------------------------------------------------------------------------

  decodif_istruzione: 
    decode_instr port map ( I_INSTR,rs1,rs2,rd,alu_operation,jump_operation,
                                   shift_operation,wb_mux,imm_mux,immediate,mr,mw );

  calcolo_PC:
    decode_pc port map ( ck,reset,enable,jump_operation,source1,immediate,curr_pc );
  
---------------------------------------------------------------------------------------------------

-- DATAPATH ---------------------------------------------------------------------------------------

	register_file:
            regfile port map (ck,reset,rs1,rf_out1,rs2,rf_out2,rd,rf_in);

    source1 <= rf_out1;
	source2 <= rf_out2 when imm_mux='0' else immediate;

	the_alu:
            alu port map ( source1,source2,alu_operation,alu_out );

        the_shifter:
            shifter port map ( source1,source2,shift_operation,shift_out );

        rf_in <= alu_out when (wb_mux="00") else shift_out when (wb_mux="01") else mem_out;			

  
  -- Accesso alle memorie esterne
        -- Indirizzo di accesso in memoria istruzioni
	I_ADDR    <= curr_pc;

        -- Indirizzo di accesso in memoria dati, e' attivo solo quando
        -- si ha una load o una store
	D_ADDR    <= immediate when (mr='1' or mw='1') else (others=>'0');

        -- Dato scritto in memoria dati, e' attivo solo quando si ha una store
	D_DATAOUT <= source1  when (mw='1') else (others=>'0');

        -- Segnali di controllo della memoria dati (Memory read, Memory Write)
        D_MR <= mr;
        D_MW <= mw;
  
        -- Dato letto dalla memoria dati
	mem_out <= D_DATAIN;

	-- Valori di Writeback, che vengono portati all'esterno per facilitare il debug del dispositivo
    -- E' fatto per comodita' non ha nessuna attinenza con il dispositivo in se'
	WB_REG   <= rd;
	WB_VALUE <= rf_in;

end struct;