LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY lpm;
USE lpm.lpm_components.ALL;

entity instr_memory is 
port( CK  : in std_logic;
      WEN : in std_logic;
      A   : in std_logic_vector(7 downto 0);
      D   : in std_logic_vector(15 downto 0);
      Q   : out std_logic_vector(15 downto 0) ); 
end instr_memory;
	
architecture memory_b of instr_memory is

  
component lpm_ram_dq
  generic( lpm_width: positive := 16;
           lpm_widthad: positive :=8;
           lpm_outdata: string:="UNREGISTERED";
           lpm_file: string:="instr_memory.mif";
           use_eab: string:="on" );
    port ( data    : in  std_logic_vector(LPM_WIDTH-1 downto 0);
	   address : in  std_logic_vector(LPM_WIDTHAD-1 downto 0);
	   inclock : in  std_logic := '0';
	   we      : in  std_logic;
	   q       : out std_logic_vector(LPM_WIDTH-1 downto 0) );
end component;

signal WE : std_logic;

begin

  WE <= not WEN;
  
  instr_mem: lpm_ram_dq
      PORT MAP ( data => D,  
		 address => A,
		 inclock => CK,  
		 we => WE,
                 q => Q);
				
end memory_b;