library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.ESD2004_types.all;

entity regfile is
    port(  ck    : in  Std_logic;
           reset  : in  Std_logic;
           ra     : in  Std_logic_vector(2 downto 0);
           a_out  : out Std_logic_vector(7 downto 0);
     	   rb     : in  Std_logic_vector(2 downto 0);
	   b_out  : out Std_logic_vector(7 downto 0);
                           
    	   rd1    : in  Std_logic_vector(2 downto 0);
	   d1_in  : in  Std_logic_vector(7 downto 0)  );    
end Regfile;

architecture behavioral of regfile is 

component rf_reg is
port (   ck, reset         : in  std_logic;
         data_in            : in  std_logic_vector(7 downto 0);
         data_out           : out std_logic_vector(7 downto 0)   );
end component;


  type bus8x8 is array (0 to 7) of std_logic_vector(7 downto 0);

  signal reg_in,reg_out : bus8x8;
  signal Lo             : Std_logic;
  
begin
  
  Registers:for i in 1 to 7 generate   
     rx : rf_reg port map (ck,reset,reg_in(i),reg_out(i));                            
  end generate Registers;

  
    -- Reg_file Reads
    --
	a_out <= reg_out(conv_integer(unsigned(ra)) );
	b_out <= reg_out(conv_integer(unsigned(rb)) );  
     
    -- Reg_file writes. Being clock-dependent, this process separates
    -- the memory access from the Writeback stage: Consequently, there is
    -- no need for an esplicit writeback register for Data or Control
    -- signals.
  
  process(rd1,d1_in,reg_out)
    begin
      for i in 1 to 7 loop
          if i = Conv_integer(unsigned(rd1)) then
             reg_in(i) <= d1_in;
          else
             reg_in(i) <= reg_out(i);
          end if;
      end loop;
  end process;

  reg_in(0)  <= ("00000000");
  reg_out(0) <= ("00000000");
  
end behavioral;


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity rf_reg is
port (   ck, reset         : in  std_logic;
         data_in            : in  std_logic_vector(7 downto 0);
         data_out           : out std_logic_vector(7 downto 0)   );
end rf_reg;

architecture behavioral of rf_reg is
begin

  process(CK, reset)
  begin
    if reset = '1' then data_out <= (others=>'0');
    elsif CK'event and CK = '1' then
     	data_out <= data_in;
    end if;
  end process;

end behavioral;