library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.ESD2004_types.all;

entity shifter is
	    port(  in_a         : in  std_logic_vector(7 downto 0);
                   in_b         : in  std_logic_vector(7 downto 0);
                   op           : in  Shift_op;
                   result       : out std_logic_vector(7 downto 0) );
end shifter;

architecture beh of shifter is
begin 
  process(op,in_a,in_b)
  variable index,count : integer range 0 to 7;

   begin     
	count := Conv_integer(unsigned(in_b(2 downto 0)));
    
	if op=sh_sll then   --shift logico a sinistra
    	SHIFT_LEFT: for i in 7 downto 0 loop
    	              if i>=count then
    	                   index := i-count;
    	                   result(i) <= in_a(index);
    	              else
    	                   result(i) <= '0';
    	              end if;
    	            end loop;  -- i            
	elsif op=sh_srl then   --shift logico destra
    	SHIFT_RIGHT_LOGICO: for i in 0 to 7 loop
           	        		    if i<=7-count then
           	        			    index:=i+count;
           	        			    result(i) <= in_a(index);
           	        		    else
									result(i) <= '0';
                               	end if;
            		        end loop;  -- i
	elsif op=sh_sra then --shift destra aritmetico
		SHIFT_RIGHT_ARITMETICO: for i in 0 to 7 loop
           	        		  	  if i<=7-count then
           	        			    index:=i+count;
           	        			    result(i) <= in_a(index);
           	        		    else
									result(i) <= in_a(7);
            	            	end if;
            		        end loop;  -- i
	else 
		 result <= (others=>'0');
	end if;     
end process; 
end beh;