library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; entity FIR is port( clk,reset,enable : in std_logic; data_in : in signed(4 downto 0); data_out : out signed(13 downto 0) ); end FIR; architecture STRUCT of FIR is component reg port( clk,reset,enable : in std_logic; data_in : in signed(4 downto 0); data_out : out signed(4 downto 0) ); end component; constant h0 : integer :=1; constant h1 : integer :=2; constant h2 : integer :=1; constant h3 : integer :=0; constant h4 : integer :=1; signal d0,d1,d2,d3,d4 : signed(4 downto 0); signal t0,t1,t2,t3,t4 : signed(9 downto 0); begin delay0 : reg port map(clk,reset,enable,data_in,d0); delay1 : reg port map(clk,reset,enable,d0,d1); delay2 : reg port map(clk,reset,enable,d1,d2); delay3 : reg port map(clk,reset,enable,d2,d3); delay4 : reg port map(clk,reset,enable,d3,d4); t0 <= d0 * conv_signed(h0,5); t1 <= d1 * conv_signed(h1,5); t2 <= d2 * conv_signed(h2,5) ; t3 <= d3 * conv_signed(h3,5); t4 <= d4 * conv_signed(h4,5); data_out <= t0+t1+t2+t3+t4; end STRUCT; library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; entity reg is port( clk,reset,enable : in std_logic; data_in : in signed(4 downto 0); data_out : out signed(4 downto 0) ); end reg; architecture BEH of reg is begin process(clk,reset) begin if reset='0' then data_out <= (others => '0'); else if clk'event and clk='1' then if enable='0' then data_out <= data_in; end if; end if; end if; end process; end BEH;