-----------------------------------------------------------------------
library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
   use IEEE.std_logic_unsigned.all;

entity OROLOGIO is
   port (
      MM     : out unsigned(5 downto 0);
      SS     : out unsigned(5 downto 0);
      CLOCK  : in std_logic;
      DEC_SEC : in std_logic;
      RESET  : in std_logic
   );
end OROLOGIO;

architecture C of OROLOGIO is
   signal MM_reg, SS_reg, next_MM, next_SS : unsigned(5 downto 0);
   signal DEC_MIN : std_logic;
begin

   process(CLOCK)
   begin
      if CLOCK'event and CLOCK='1' then
         if RESET = '1' then
            MM_reg <= conv_unsigned(2,6);
            SS_reg <= conv_unsigned(0,6);
         else
            MM_reg <= next_MM;
            SS_reg <= next_SS;
         end if;
      end if;
   end process;

   process(SS_reg, DEC_SEC)
   begin
      if DEC_SEC = '0' then
         next_SS <= SS_reg;
      elsif (SS_reg = conv_unsigned(0,6)) then
         next_SS <= conv_unsigned(59,6);
      else
         next_SS <= SS_reg - conv_unsigned(1,6);
      end if;
    end process;

   process(MM_reg, DEC_MIN)
   begin
      if DEC_MIN = '0' then
         next_MM <= MM_reg;
      elsif (MM_reg = conv_unsigned(0,6)) then
         next_MM <= conv_unsigned(2,6);
      else
         next_MM <= MM_reg - conv_unsigned(1,6);
      end if;
    end process;

  DEC_MIN <= '1' when (SS_reg = conv_unsigned(0,6) and DEC_SEC = '1') else '0';

MM <= MM_reg;
SS <= SS_reg;
  
end C;


---------------------

library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
   use IEEE.std_logic_unsigned.all;

entity TIMER is
   port (
      RESET : in std_logic;
      BUTTON : in std_logic;
      MM    : out unsigned(5 downto 0);
      SS    : out unsigned(5 downto 0);
      CLOCK : in std_logic;
      SOUND : out std_logic
   );
end TIMER;

architecture A of TIMER is
   component OROLOGIO
   port (
      MM     : out unsigned(5 downto 0);
      SS     : out unsigned(5 downto 0);
      CLOCK  : in std_logic;
      DEC_SEC : in std_logic;
      RESET  : in std_logic
   );
   end component;

  component clk_divider
  port ( clk   : in  std_logic;
         t1Hz : out std_logic;
         res   : in  std_logic);
  end component;


   type timer_state is ( stop, go, bell );
   signal present_state, next_state : timer_state;
   signal decrement_timer : std_logic;
   signal internal_MM, internal_SS : unsigned(5 downto 0);
   signal wave1Hz : std_logic;
   signal timeover : std_logic;
begin

   O0 : orologio port map(MM => internal_MM, SS => internal_SS, CLOCK => CLOCK, 
                          DEC_SEC => decrement_timer, RESET => RESET);

   CD0 : clk_divider port map (clk => CLOCK, t1Hz => wave1Hz, res => RESET );

   process(CLOCK)
   begin
      if CLOCK'event and CLOCK='1' then
         if RESET = '1' then
            present_state <= stop;
         else
            present_state <= next_state;
         end if;
      end if;
   end process;
   

   process(present_state, BUTTON, timeover, wave1Hz)
   begin

      case present_state is
         when stop =>
            decrement_timer <= '0';
            sound <= '0';
            
            if BUTTON = '1' then
               next_state <= go;
            else 
               next_state <= stop;
            end if;

          when go =>
             decrement_timer <= wave1Hz;
             sound <= '0';

             if timeover = '1' then
               next_state <= bell;
             elsif BUTTON = '1' then
                next_state <= stop;
             else
                next_state <= go;
             end if;

           when bell =>
              decrement_timer <= '0';
              sound <= '1';

              if BUTTON = '1' then
                 next_state <= stop;
              else next_state <= bell;
              end if;

           when others =>
               next_state <= stop;
               decrement_timer <= '0';
               sound <= '0';
       end case;
end process;

   timeover <= '1' when (internal_MM = conv_unsigned(0,6) and internal_SS = conv_unsigned(0,6)) else '0';

   MM <= internal_MM;
   SS <= internal_SS;

end A;


----------------------------


library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all;
  use IEEE.std_logic_unsigned.all;

entity clk_divider is
  port ( clk   : in  std_logic;
         t1Hz : out std_logic;
         res   : in  std_logic);
end clk_divider;

architecture A of clk_divider is
   signal count, new_count : unsigned(13 downto 0);
   signal reset_counter : std_logic;
   signal last_value : std_logic;
begin
  
   process(count)
   begin
      new_count <= count + conv_unsigned(1,14);
   end process;

   reset_counter <= res or last_value;

   process(clk)
   begin
      if clk'event and clk = '1' then
         if reset_counter = '1' then
            count <= conv_unsigned(0,14);
         else count <= new_count;
         end if;
      end if;
   end process;

   last_value <= '1' when count = conv_unsigned(5,14) else '0';
   t1Hz <= last_value;

end A;